Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date         : Wed May 28 14:34:17 2025
| Host         : DESKTOP-A5BALAG running 64-bit major release  (build 9200)
| Command      : report_timing -file timing_report_braun.txt
| Design       : Eight_bit_Braun
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
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Timing Report

Slack (VIOLATED) :        -8.139ns  (required time - arrival time)
  Source:                 A0
                            (input port clocked by virtclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            P14
                            (output port clocked by virtclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             virtclk
  Path Type:              Max at Slow Process Corner
  Requirement:            10.000ns  (virtclk rise@10.000ns - virtclk rise@0.000ns)
  Data Path Delay:        14.114ns  (logic 4.783ns (33.891%)  route 9.331ns (66.109%))
  Logic Levels:           12  (IBUF=1 LUT6=10 OBUF=1)
  Input Delay:            2.000ns
  Output Delay:           2.000ns
  Clock Uncertainty:      0.025ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock virtclk rise edge)    0.000     0.000 r  
                         ideal clock network latency
                                                      0.000     0.000    
                         input delay                  2.000     2.000    
    U14                                               0.000     2.000 r  A0 (IN)
                         net (fo=0)                   0.000     2.000    A0
    U14                  IBUF (Prop_ibuf_I_O)         0.936     2.936 r  A0_IBUF_inst/O
                         net (fo=21, routed)          1.543     4.479    A0_IBUF
    SLICE_X0Y8           LUT6 (Prop_lut6_I4_O)        0.124     4.603 r  P4_OBUF_inst_i_5/O
                         net (fo=9, routed)           0.641     5.244    C3
    SLICE_X0Y9           LUT6 (Prop_lut6_I5_O)        0.124     5.368 r  P6_OBUF_inst_i_12/O
                         net (fo=2, routed)           0.976     6.344    u_Model11/XOR_out1__0
    SLICE_X0Y7           LUT6 (Prop_lut6_I1_O)        0.124     6.468 r  P6_OBUF_inst_i_6/O
                         net (fo=4, routed)           0.783     7.251    C3_2
    SLICE_X2Y9           LUT6 (Prop_lut6_I2_O)        0.124     7.375 r  P8_OBUF_inst_i_16/O
                         net (fo=3, routed)           0.471     7.846    C3_3
    SLICE_X4Y10          LUT6 (Prop_lut6_I0_O)        0.124     7.970 r  P9_OBUF_inst_i_13/O
                         net (fo=3, routed)           0.597     8.568    S1_16
    SLICE_X5Y12          LUT6 (Prop_lut6_I2_O)        0.124     8.692 r  P9_OBUF_inst_i_6/O
                         net (fo=7, routed)           0.630     9.321    C4_5
    SLICE_X4Y13          LUT6 (Prop_lut6_I2_O)        0.124     9.445 r  P12_OBUF_inst_i_7/O
                         net (fo=3, routed)           0.867    10.312    C4_6
    SLICE_X3Y18          LUT6 (Prop_lut6_I0_O)        0.124    10.436 r  P12_OBUF_inst_i_4/O
                         net (fo=2, routed)           0.646    11.082    S1_25
    SLICE_X1Y18          LUT6 (Prop_lut6_I4_O)        0.124    11.206 r  P14_OBUF_inst_i_2/O
                         net (fo=2, routed)           0.465    11.671    C2_13
    SLICE_X1Y19          LUT6 (Prop_lut6_I0_O)        0.124    11.795 r  P14_OBUF_inst_i_1/O
                         net (fo=1, routed)           1.712    13.507    P14_OBUF
    P18                  OBUF (Prop_obuf_I_O)         2.607    16.114 r  P14_OBUF_inst/O
                         net (fo=0)                   0.000    16.114    P14
    P18                                                               r  P14 (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock virtclk rise edge)   10.000    10.000 r  
                         ideal clock network latency
                                                      0.000    10.000    
                         clock pessimism              0.000    10.000    
                         clock uncertainty           -0.025     9.975    
                         output delay                -2.000     7.975    
  -------------------------------------------------------------------
                         required time                          7.975    
                         arrival time                         -16.114    
  -------------------------------------------------------------------
                         slack                                 -8.139    




